Power consumption is a concern in most circuit designs, particularly those that are to be battery-powered. Circuit designs should achieve the lowest possible power consumption while achieving defined performance targets. Timing is a major concern in all IC designs, because circuits will not operate properly unless signals can propagate properly through them. Consequently, “timing signoff” is a required step in the designing of a circuit, particularly an IC, and involves using a signoff analysis tool to determine the time that signals will take to propagate through the circuit. If propagation time is inadequate, critical paths in the circuit may have to be modified, or the circuit may have to operate at a slower speed. Power and timing objectives are often at odds; faster devices usually require more power than slower devices, and vice versa.
Electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, are used by electronic circuit designers to create representations of the cells in a particular circuit and the conductors (called “interconnects” or “nets”) that couple the cells together. EDA tools allow designers to construct a circuit design and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern, very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
Many EDA tool companies offer EDA tools that perform both power and timing optimization. These combined power and timing optimization tools employ approximate circuit models and parameters to represent the circuit design and are used well before timing signoff. Timing signoff then becomes an iterative process of using the signoff analysis tool to analyze timing on an accurate representation of the finished circuit design, re-optimize for power and timing using the combined optimization tool and reanalyze using the signoff analysis tool until further optimization becomes unfruitful. Some EDA tool companies offer power optimization tools that run in conjunction with the signoff analysis tool. However, these power optimization tools must be integrated into timing signoff, requiring users to purchase and learn the additional power optimization tool to design a circuit and creating coordination issues between the power optimization tool and the signoff analysis tool which require additional turnaround time to resolve. Such power optimization tools also do not readily adapt to requirements specific to a particular circuit design.